SLT Engineer

Role Overview The System Level Test Engineer will own the design, development, and validation of System Level Tests (SLT) from a software perspective. This role involves close collaboration with silicon design, system validation, and vendor teams to ensure high-quality testing, performance optimization, and scalable SLT solutions for high-power silicon platforms. Key Responsibilities • Own the design and validation of System Level Tests (SLT) from a software standpoint. • Develop custom system-level tests to enable effective screen testing for SLT. • Collaborate with chip design and system validation teams to create test plans for system-to-tester correlation, optimizing power and performance. • Develop software/code to interface SLT handlers, test controllers, and peripherals, including temperature control units. • Write test methods, scripts, and automation code to build a complete test flow covering all system-level tests defined by the system validation team. • Drive SLT testing in High Volume Manufacturing (HVM) environments. • Support day-zero bring-up of new silicon at the system level. • Lead SLT handler selection and enablement, working closely with multiple vendors and OSAT partners. • Support failure analysis, RMA, reliability testing, and production readiness activities. Required Skills & Technologies • System Level Test (SLT) • High Volume Manufacturing (HVM), New Product Introduction (NPI) • ATE and OSAT environments • Network topology and connectivity (hardware & software) • Bench testing, Burn-In, HTOL, RMA processes • Experience testing high-power IPs: • TPUs, CPUs, GPUs • High-speed interface testing: • PCIe, Ethernet, SerDes • Programming & Scripting: • C#, C/C++ • Python • PERL • .NET Framework • Security provisioning and Fuse programming • Experience with mission-mode testing and characterization Preferred Experience • Hands-on experience in systems validation and system-level testing • Experience driving SLT solutions from development to production • Vendor coordination and SLT handler customization experience • Exposure to large-scale silicon platforms and complex system environments