Comprehensive Resources Inc

UFS Engineer

⭐ - Featured Role | Apply direct with Data Freelance Hub
This role is for a UFS Engineer in San Jose, CA, offering a contract length of "unknown" and a pay rate of "unknown." Requires 2-7 years of experience, strong skills in UFS, FPGA, Zebu, Python, and validation testing.
🌎 - Country
United States
πŸ’± - Currency
$ USD
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πŸ’° - Day rate
Unknown
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πŸ—“οΈ - Date
April 1, 2026
πŸ•’ - Duration
Unknown
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🏝️ - Location
On-site
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πŸ“„ - Contract
Unknown
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πŸ”’ - Security
Unknown
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πŸ“ - Location detailed
San Jose, CA
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🧠 - Skills detailed
#Perl #Python #Scripting #IP (Internet Protocol) #Data Encryption #Automation #Storage #Linux
Role description
Job Title :UFS Engineer Location: San Jose,CA Key skills: Zebu, FPGA ,UFS , ARM β€’ Develop and execute verification test plans for UFS host IP within a System-on-Chip (SoC) environment using tools like emulation platforms (Veloce, ZEBU, HAPs). β€’ Debug failures using waveform viewers and log files to isolate and root cause issues in UFS protocols and bus interconnects β€’ Create prepost silicon Validation C bases Test content . β€’ Enable firmware-driven validation on emulation platforms to integrate UFS driver-level software with hardware. β€’ Validate that UFS IP meets power, performance, and throughput specifications (e.g., UFS 3.x/4.x/5.x) Capture and analyze waveforms on Zebu (or similar emulation platforms) to root‑cause design and integration issues. 2 to 7 years of experience β€’ Deep understanding of UFS standards (UFS host controller interface β€’ Create pre/post silicon Validation C bases Test content β€’ Strong scripting skills in Python, Perl, or TCL for automation β€’ Hands-on experience with hardware emulation (Zebu/Veloce) and FPGA prototyping. β€’ Validating how the UFS IP interacts with other SoC components, including the southbridge, memory controllers, and bus interconnects (e.g., AXI, AHB). β€’ Identifying and fixing RTL bugs in a pre-silicon environment using waveform viewers (e.g., Verdi) and log files β€’ Ensuring the UFS IP correctly implements features like data encryption, power management, and high-speed data transfer (M-PHY/UniPro). β€’ Developing performance models (often in SystemC/TLM) to analyze and optimize the storage subsystem's throughput and latency. β€’ Develop and execute test plans in C to validate the Features In depth knowledge of one or more peripheral protocols and specifications Β· Bare metal/Linux driver development, Firmware development.