System IP / RTL Design Engineer

Job Description Job Title: System IP/RTL Design Engineer Position Description: Protingent Staffing has an exciting contract System IP / RTL Design Engineer opportunity with our client located in Austin, TX. Job Responsibilities: • Work on RTL design of System IP blocks • Work independently while closely collaborating with other designers as well as members of verification, physical design, performance and power teams • Work on developing and maintaining Front-End Tools, Flows and Methodologies • Work on creating scripts that automate repetitive daily tasks of team members • Support Silicon bring-up activities Job Qualifications: • Proficient in RTL design using Verilog and System Verilog • Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis • Excellent debug and problem-solving skills. Experienced in Silicon bring-up activities • Experienced in timing and coverage closure • Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting • Prior experience of having worked with interconnects, caches and/or cache coherency would be an added advantage. Nice To Have: • Verilog/System Verilog • GIT • Perl • Python • Tcl/Tk • C/C++ • Jenkins, Jira. Job Details: • Job Type: Contract • Pay Range: $80 - $90 an hour. • Location: Austin, TX (Onsite). Benefits Package: Protingent offers competitive salaries, insurance plan options (HDHP plan or POS plan), education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO), and an administered 401k plan. About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.