Tranzeal Incorporated
SystemC Modelling Engineer
⭐ - Featured Role | Apply direct with Data Freelance Hub
This role is for a SystemC Modelling Engineer with a remote contract, requiring expertise in SystemC, TLM, VHDL/Verilog, Python, and C++. Key skills include simulation tools, debugging, and embedded systems architecture. Strong communication and problem-solving abilities are essential.
🌎 - Country
United States
💱 - Currency
$ USD
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💰 - Day rate
Unknown
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🗓️ - Date
February 7, 2026
🕒 - Duration
Unknown
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🏝️ - Location
Remote
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📄 - Contract
Unknown
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🔒 - Security
Unknown
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📍 - Location detailed
United States
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🧠 - Skills detailed
#Perl #Python #IP (Internet Protocol) #Embedded Systems #Debugging #Linux #Version Control #GIT #C++ #Scripting
Role description
Role: SystemC Modelling Engineer
Location: Remote
Mandatory required:
SystemC Modelling Engineer
SystemC & TLM
Hardware Description Languages (HDLs): VHDL or Verilog
Python
Required Skills:
SystemC & TLM (Transaction Level Modeling)
C++ (Proficient level, including object-oriented design principles)
Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with)
Simulation Tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Graphics QuestaSim)
Debugging Tools (e.g., GDB, DVE)
Scripting Languages (Python, Perl, or similar)
Version Control Systems (Git)
Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols)
Communication (Excellent written and verbal communication skills)
Problem-Solving (Strong analytical and problem-solving abilities)
Team Collaboration (Ability to work effectively in a team environment)
Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc)
Porting the embedded operating system (Linux, VXWorks, Android ) on the virtual prototype, developing the device drivers etc.
Verification of models at IP & SoC level.
Develop regress able self-checking test suites using C/ARM assembly.
Develop System Level Flows and Methodologies using virtual prototypes
Please share your updated resume at subhd@tranzeal.com
Role: SystemC Modelling Engineer
Location: Remote
Mandatory required:
SystemC Modelling Engineer
SystemC & TLM
Hardware Description Languages (HDLs): VHDL or Verilog
Python
Required Skills:
SystemC & TLM (Transaction Level Modeling)
C++ (Proficient level, including object-oriented design principles)
Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with)
Simulation Tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Graphics QuestaSim)
Debugging Tools (e.g., GDB, DVE)
Scripting Languages (Python, Perl, or similar)
Version Control Systems (Git)
Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols)
Communication (Excellent written and verbal communication skills)
Problem-Solving (Strong analytical and problem-solving abilities)
Team Collaboration (Ability to work effectively in a team environment)
Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc)
Porting the embedded operating system (Linux, VXWorks, Android ) on the virtual prototype, developing the device drivers etc.
Verification of models at IP & SoC level.
Develop regress able self-checking test suites using C/ARM assembly.
Develop System Level Flows and Methodologies using virtual prototypes
Please share your updated resume at subhd@tranzeal.com
