Formal Verification Engineer
Responsibilities:
• Serve as a technical leader in Formal Verification across IP, subsystem, and SoC levels.
• Develop, implement, and promote best-in-class Formal Verification methodologies, driving adoption across both block and top-level verification teams.
• Collaborate closely with architecture and design teams to derive formal specifications and integrate them into the design and verification process.
• Define and manage the scope of formal verification activities, including environment creation, coverage closure, and deployment of advanced formal techniques.
• Build scalable and reusable formal verification environments to enhance efficiency and maintainability.
• Evaluate, adopt, and integrate EDA tools and solutions that support advanced Formal Verification capabilities.
• Provide mentorship and technical training to engineering teams on formal tools, techniques, and methodology best practices.
Minimum Qualifications:
• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
• 5+ years of hands-on experience in Formal Verification.
• In-depth experience with formal verification techniques such as datapath verification, sequential equivalence checking, X-propagation analysis, clock gating, and connectivity validation.
• Strong grasp of complexity reduction and abstraction strategies in Formal Verification.
• Demonstrated analytical problem-solving skills, particularly in addressing complex design challenges.
• Proven ability to work collaboratively with cross-functional teams including architecture, design, and verification.
• Proficiency in hardware description and assertion languages (SystemVerilog, SVA).
• Solid scripting skills using Python, Perl, or Tcl.
• Hands-on experience with leading formal verification tools such as Cadence JasperGold or Synopsys VC Formal.
Preferred Qualifications:
• Ability to quickly interpret specifications and derive meaningful formal properties and behaviors.
• Experience verifying complex compute-intensive blocks (DSP, CPU, GPU, or custom accelerators) using formal methods.
• Background in verifying clock domain crossings, low-power designs, and IP-XACT-based register files using formal techniques.
• Experience working on large-scale SoC projects and driving formal sign-off at scale.
• Familiarity with end-to-end flow automation from specification to formal closure.
• Experience using simulators and waveform analysis tools for debug and validation.
Responsibilities:
• Serve as a technical leader in Formal Verification across IP, subsystem, and SoC levels.
• Develop, implement, and promote best-in-class Formal Verification methodologies, driving adoption across both block and top-level verification teams.
• Collaborate closely with architecture and design teams to derive formal specifications and integrate them into the design and verification process.
• Define and manage the scope of formal verification activities, including environment creation, coverage closure, and deployment of advanced formal techniques.
• Build scalable and reusable formal verification environments to enhance efficiency and maintainability.
• Evaluate, adopt, and integrate EDA tools and solutions that support advanced Formal Verification capabilities.
• Provide mentorship and technical training to engineering teams on formal tools, techniques, and methodology best practices.
Minimum Qualifications:
• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
• 5+ years of hands-on experience in Formal Verification.
• In-depth experience with formal verification techniques such as datapath verification, sequential equivalence checking, X-propagation analysis, clock gating, and connectivity validation.
• Strong grasp of complexity reduction and abstraction strategies in Formal Verification.
• Demonstrated analytical problem-solving skills, particularly in addressing complex design challenges.
• Proven ability to work collaboratively with cross-functional teams including architecture, design, and verification.
• Proficiency in hardware description and assertion languages (SystemVerilog, SVA).
• Solid scripting skills using Python, Perl, or Tcl.
• Hands-on experience with leading formal verification tools such as Cadence JasperGold or Synopsys VC Formal.
Preferred Qualifications:
• Ability to quickly interpret specifications and derive meaningful formal properties and behaviors.
• Experience verifying complex compute-intensive blocks (DSP, CPU, GPU, or custom accelerators) using formal methods.
• Background in verifying clock domain crossings, low-power designs, and IP-XACT-based register files using formal techniques.
• Experience working on large-scale SoC projects and driving formal sign-off at scale.
• Familiarity with end-to-end flow automation from specification to formal closure.
• Experience using simulators and waveform analysis tools for debug and validation.
