System-on-Chip Design Engineer

Role: SOC Design Verification Engineer Location: Santa Clara , CA Hybrid – 3 days in office Mandatory Skills & Proficiencies: 1. UVM/SystemVerilog – Expert proficiency (Priority: 1) 1. Synopsys/Cadence EDA Design & Verification Tools – Expert proficiency (Priority: 1) 1. Python/TCL/Perl Scripting – Intermediate proficiency (Priority: 3) Experience Required: • 8–10 years of hands-on experience in ASIC Design Verification using SystemVerilog/UVM. • Proven record of first-pass success in ASIC development cycles. • Strong background in building and executing verification environments from scratch. • Familiarity with SV Assertions, Formal Verification, and Emulation. • Experience in using EDA tools for verification flow automation. Preferred Experience: • Verification of GPU/CPU or Data Center-related designs (Video, AI/ML, Networking). • Experience with PCIe, DDR, Ethernet high-speed interface verification. • Version control tools – Git, Hg, SVN. • Strong cross-functional collaboration skills (Design, Model, Emulation, Silicon Validation teams). Key Responsibilities: • Define and implement SoC verification plans and build test benches for sub-system/SoC verification. • Develop functional tests as per the verification plan. • Drive Design Verification to closure using verification metrics (functional/code coverage). • Debug and resolve functional failures in collaboration with design teams. • Contribute to continuous process improvements using latest verification tools and methodologies.